module pc(
  input             clk,
  input             rst,
  input             we,
  input             br,
  input      [31:2] br_dst,
  output reg [31:2] q
);

always @(posedge clk) begin
  if (rst) begin
    q <= 30'b0;
  end else begin
    if (we) begin
      q <= br ? br_dst : q + 30'b1 ;
    end
  end
end

endmodule
